https://danielmangum.com/categories/moss/ Recent content in moss on Daniel Mangum Hugo -- gohugo.io en Fri, 03 Nov 2023 00:10:34 -0600 https://danielmangum.com/posts/setup-verible-verilog-neovim/ Fri, 03 Nov 2023 00:10:34 -0600 https://danielmangum.com/posts/setup-verible-verilog-neovim/ I have been using Vivado for moss RTL development, which, despite its notoriously large install size, offers a fairly decent developer experience. Or maybe I have just been using it for too long. I’m not sure I would have said this a few months ago. However, I still prefer to write Verilog in Neovim, as it allows me to use vim motions, as well as switch between RTL and software code without changing my workflow. https://danielmangum.com/posts/how-luts-used-storage-fpga/ Sat, 14 Oct 2023 00:10:34 -0600 https://danielmangum.com/posts/how-luts-used-storage-fpga/ If you are interested in what went into writing this blog post, you can view a replay of the livestream here. In a recent post we explored when Vivado inferred Block RAM (BRAM) for memories in FPGA designs, and when it used distributed RAM instead. While it is somewhat obvious why BRAM can be used for memory in an FPGA (i.e. it is literally a discrete memory element), distributed RAM is a bit more complicated. https://danielmangum.com/posts/value-livestreaming-long-term/ Fri, 06 Oct 2023 00:10:34 -0600 https://danielmangum.com/posts/value-livestreaming-long-term/ This is less of a blog post, and more of a collection of Friday thoughts that occurred to me on my morning run. Last night I was livestreaming some work on a new moss blog post in which I describe the use of Look-Up Tables (LUTs) as storage elements on an FPGA (this will be published in a few days). However, I ended up spending the majority of the time scouring the internet for documentation on the relationship between 5-input LUTs (LUT5) and 6-input LUTs (LUT6) on Xilinx 7 Series FPGAs. https://danielmangum.com/posts/when-vivado-infer-bram/ Sun, 01 Oct 2023 00:10:34 -0600 https://danielmangum.com/posts/when-vivado-infer-bram/ If you are interested in what went into writing this blog post, you can view a replay of the livestream here. As I’ve been working on the logic design for moss, I have been regularly investigating how Vivado translates the Verilog RTL (Register Transfer Level) source into Basic Elements of Logic (BELs), a process known as synthesis. BELs represent the physical components on an FPGA that can be used to implement a design. https://danielmangum.com/posts/microprocessors-tiny-cant-fit-in-head/ Sat, 02 Sep 2023 00:10:34 -0600 https://danielmangum.com/posts/microprocessors-tiny-cant-fit-in-head/ I have not been able to make as much progress on moss over the last 14 days or so as I would like, in large part because of limited time due to getting some exciting work across the finish line at $dayjob. However, whenever I find myself limited in the amount of “hands on keyboard” time I have to spend on a project, I try to invest more of my idle brain time (IBT, if you will) thinking about the next stages of development, as well as higher level long-term goals. https://danielmangum.com/posts/retrospective-sparc-register-windows/ Mon, 21 Aug 2023 00:10:34 -0600 https://danielmangum.com/posts/retrospective-sparc-register-windows/ As I work on moss and research modern processor design patterns and techniques, I am also looking for patterns and techniques from the past that, for one reason or another, have not persisted into our modern machines. While on a run this week, I was listening to an old Oxide and Friends episode where Bryan, Adam, and crew were reminiscing on the SPARC instruction set architecture (ISA). SPARC is a reduced instruction set computer (RISC) architecture originally developed by Sun Microsystems, with the first machine, the SPARCstation1 (a. https://danielmangum.com/posts/how-to-dissect-critical-hackernews/ Wed, 09 Aug 2023 00:10:34 -0600 https://danielmangum.com/posts/how-to-dissect-critical-hackernews/ Note: while I was writing this post, Julia Evans published a wonderful entry on her blog entitled Some tactics for writing in public. I highly recommend reading as it includes some wonderful guidance about how to preempt some of the discussion I reference in this post, as well as a short but highly relevant section on analyzing negative comments. You can think of this post as putting some of that theory into practice. https://danielmangum.com/posts/single-cycle-rv64-register-file/ Fri, 04 Aug 2023 00:10:34 -0600 https://danielmangum.com/posts/single-cycle-rv64-register-file/ It’s a simple question really: how can you read and write to the same register in a single-cycle processor? If you have spent most of your life working with software, it is tempting to think of all events as happening sequentially. However, that sequential model that we have become so familiar with as software engineers is really an abstraction that hardware offers to us to help our simple brains reason about logic. https://danielmangum.com/posts/single-cycle-multicycle-processor-performance/ Fri, 28 Jul 2023 00:10:34 -0600 https://danielmangum.com/posts/single-cycle-multicycle-processor-performance/ If you read most literature about processor design, you’ll inevitably be presented with three broad categories of CPU architectures: Single-Cycle Multicycle Pipelined We’ll just be focusing on the first two for today. In fact, my favorite introductory book on computer architecture, Computer Organization and Design (Patterson & Hennessy) progresses through Chapter 4: The Processor by explaining these three models in sequence. The first big idea can be synthesized into the following logic: https://danielmangum.com/posts/why-create-new-isa/ Fri, 21 Jul 2023 00:10:34 -0600 https://danielmangum.com/posts/why-create-new-isa/ TL;DR: even if you’re not being pragmatic, you probably don’t need to. One of the things I have been thinking about while starting to work on moss again is whether I should implement one of the many RISC-V flavors, or whether I should design an entirely new instruction set architecture (ISA). Designing a new one might seem like the ultimate bike-shedding effort, and if my immediate goal was getting something useful into production, I almost certainly would not embark on the journey. https://danielmangum.com/posts/a-three-year-bet-on-chip-design/ Wed, 19 Jul 2023 00:10:34 -0600 https://danielmangum.com/posts/a-three-year-bet-on-chip-design/ I turn 27 years old today, which feels both very old and very young. 30 is often seen as a milestone, perhaps because you have spent nearly a decade operating as an “adult”, but likely are still considered in the earlier part of your career. I am a firm believer that doing most things of significance takes at least 3 years, which makes 27 a good time to decide to commit to “doing something before you are 30”.