The Zmmul Extension
Tonight’s @risc_v Tip:
The Zmmul extension species only the multiplication instructions from the M extension, allowing constrained RISC-V implementations to opt not to support division. The spec calls out FPGAs as an example, as many have built-in multiplier hardware.
You’ll notice that MULW is only supported on RV64 implementations. This instruction multiplies the lower 32 bits (i.e. “Multiply Word”) of rs1 and rs2 and places the sign-extension of the lower 32 bits of the result in rd.
