Today’s @risc_v Tip:
FENCE instruction is defined as part of the base ISA and allows for explicit ordering of instructions prior to (“predecessor set”) and following (“successor set”). Types of instructions to be ordered are specified in each set using the P and S bits.
Note that it is common to just see a plain
fence in RISC-V assembly, which is actually a pseudoinstruction that maps to
fence iorw, iorw. In practice, we typically want all successor memory operations to occur after all predecessors when specifying explicit ordering.