Posts

October 14, 2023 How LUTs Are Used as Storage Elements on an FPGA
October 6, 2023 The Value of Livestreaming Long-Term Projects
October 1, 2023 When Does Vivado Infer BRAM?
September 2, 2023 Microprocessors Are Tiny, But They Can’t Fit in Your Head
August 21, 2023 A Brief Retrospective on SPARC Register Windows
August 9, 2023 How To Dissect a Critical HackerNews Comment
August 4, 2023 A Single-Cycle 64-Bit RISC-V Register File
July 28, 2023 Single-Cycle and Multicycle Do Not Describe Processor Performance
July 21, 2023 Why Create a New Instruction Set Architecture?
July 19, 2023 A Three Year Bet on Chip Design
May 30, 2023 RISC-V Bytes: Semihosting with Zephyr on an ESP32
April 28, 2023 RISC-V Bytes: Zephyr Before Main
April 17, 2023 RISC-V Bytes: Zephyr on the ESP32
April 9, 2023 RISC-V Bytes: Exploring a Custom ESP32 Bootloader
April 6, 2023 Do you want to take a leap of faith?
March 18, 2023 Where does the kubelet mount volumes?
February 13, 2023 K8s ASA: Watching and Caching
January 23, 2023 K8s ASA: The Storage Interface
January 16, 2023 Welcome to Kubernetes API Server Adventures
December 27, 2022 RISC-V Bytes: Timer Interrupts